STM32F407IGT6 개발보드는 Hi-Speed USB, SRAM, NAND Flash, 이더넷, 1.3 메가픽셀 CMOS 카메라, SD, 3.2인치 TFTLCD 모듈, 오디오포트 등으로구성되어 있습니다. 특히 ARM 32-bit Cortex ™-M3 CPU(ART Accelerator ™) ㄴ는 120MHz 주파수로 내부 플래쉬 제로웨이트(zero wait) 동작이 가능하여 최대 150DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) 성능을 낼수 있습니다.
Kernel: ARM 32-bit Cortex ™-M3 CPU, adaptive real-time accelerator (ART Accelerator ™) allows the program to the execution of up to 120MHz frequency in Flash to achieve zero wait state operation performance, built-in memory protection unit, to achieve Up to 150DMIPS/1.25DMIPS/MHz (Dhrystone 2.1) performance.
memory : Up to 1 Mbyte of of Flash memory
512 bytes of the OTP memory
Up to 128 + 4 Kbytes of of of SRAM
flexible static memory controller supports Compact Flash, SRAM, PSRAM, NOR and of NAND memories
LCD parallel interface modes, 8080/6800
Clock, reset and power management
1.65 to 3.6 V application supply and I / Os
POR, PDR, the PVD and BOR
4 to 26 MHz, the crystal oscillator
Internal 16 MHz factory-trimmed RC (1% accuracy at 25 ° C)
32 kHz, oscillator for RTC with calibration
Internal 32 kHz RC with calibration
Low power Sleep, Stop and Standby modes
VBATsupply for RTC, 20 × 32 bit backup registers, and optional 4 KB backup SRAM
3x12-bit, 0.5μs the A / D converter • up to 24 channels
up to 6 MSPS, in the triple interleaved the mode
2x12-bit D / A converter
DMA : Universal 16-the stream DMA controller with centralized FIFOs. And burst support
Up to 17 timers :Up to twelve 16-bit and two 32-bit Use the timers, up to 120 MHz, each with up to 4 the IC / OC / PWM or The pulse counter and quadrature (incremental is) encoder to the input
debug mode: Serial of wire debug (SWD-) & the JTAG the interfaces
the Cortex-M3 Embedded Trace Macrocell ™
Up to 140 I / O port with interrupt function:
Up to 136 fast the I / Os up to 60 MHz
Up to 138 5 V-tolerant I / Os
Up to 15 communication interfaces
Up to 3 × I2C interfaces (SMBus / the PMBus)
Up to 4 USARTs and 2 UARTs (7.5 Mbit / s, ISO 7816 interface, LIN, IrDA, modem control)
Up to 3 SPIs (30 Mbit / s), 2 with muxed I2S to achieve audio class accuracy via audio PLL or external PLL
2 × the CAN the interfaces (2.0B Active)
the SDIO interface
Advanced interconnect • USB 2.0 full-speed device / host / OTG controller with on-chip the PHY
USB 2.0 high-speed/full-speed device / host / OTG controller with dedicated DMA, on-chip full-speed PHY and ULPI
10/100 Ethernet MAC with dedicated the DMA: Support hardware IEEE 1588v2, the MII / RMII
8 to 14-bit parallel camera interface: speed up to 48M bytes / s
CRC calculation unit
96-bit unique ID
simulation of the random number generator
16M bit high-speed asynchronous CMOS static RAM
4G Bit of NAND the Flash
IIC EEPROM
20-pin 2.54 pitch JTAG interface
10/100M Ethernet interface (MII, RMII two configuration mode)
USB2.0 high speed master-slave device interface (mini)